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Olivia Weng
hls4ml-tinyml
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skip-connections
690b8d1c
·
fix HLSModel remove_node so that it can handle rewiring multiple next nodes
·
May 14, 2022
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fifo_depth_opt
default
protected
5c0ad77f
·
Fix bug w/ clock connection that stopped the QSPI boot
·
Mar 09, 2022
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fifo_depth_opt_dev
83008127
·
Use SystemVerilog define to control EEMBC setup
·
Mar 03, 2022
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arty_fifo
5f3b4683
·
remove prints
·
Mar 01, 2022
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test_all_prs
60799059
·
small fixes
·
Feb 22, 2022
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div_by_256_patch
3590aa4f
·
remove unnecessary patches
·
Feb 21, 2022
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qdense_batchnorm
8b494a22
·
Update core.py
·
Feb 21, 2022
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gdg/axi-m
d1dab8df
·
Merge pull request #5 from GiuseppeDiGuglielmo/gdg/axi-m
·
Feb 08, 2022
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fifo_depth_opt_rebase
fcfdcdf6
·
add back cppname
·
Jan 25, 2022
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